1. Technical Field of the Invention
The present invention relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to a partitioned source line architecture for read-only memory (ROM).
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that various types of circuitry such as analog blocks, non-volatile memory (e.g., read-only memory or ROM), random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take several staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory, including ROM, is a key technology driver for SOC design. It is also well known that leakage and power consumption are two major factors in designing a high performance ROM core, especially where the device geometries continue to shrink. In typical ROM architectures, a transistor is placed at the intersection of every bitline (BL) and wordline (WL) with the transistor's gate being connected to the WL. Depending on the actual ROM code to be programmed, in one implementation, the transistor of the bit cell is either connected to the BL (for storing a binary 0) or left open (for storing a binary 1).
It should be appreciated that as the number of binary 0's on a BL increases, its capacitance also increases because of the parasitic diffusion capacitance of the transistor's drain connected thereto. It is possible that in some instances the ROM code to be programmed may have a large number of 0's on one or more BLs, resulting in degraded performance with respect to both leakage and power. Further, even where a virtual ground array is provided that utilizes precharged decoded source lines, only static leakage is effectively reduced. On the other hand, since each source line per I/O needs to make a full swing in a decoded source line architecture, the source lines can be a major power consuming component in a ROM with decoded source lines, especially where a large number of I/Os are provided. In a worst-case scenario, a source line may be associated with a column of storage cells having all zeros, thereby maximizing capacitance and power consumption. Thus, the issues of functional leakage (i.e., leakage during an access operation when a source line is driven low) and power consumption continue to remain unaddressed.